This invention relates to a technique applied to semiconductor integrated circuits, and which is particularly effective when applied to a semiconductor integrated circuit provided with a logic array. For example, the present invention can be applied effectively to a PLA (Programmable Logic Array) consisting of a logical product (AND or NAND) gate array and a logical summation (OR or NOR) gate array.
The inventors of the present invention have clarified that the following problems are encountered in semiconductor integrated circuit techniques, particularly in PLA circuit techniques.
An outline of a PLA will first be given briefly. A PLA usually consists of a logical product gate array and a logical summation gate array. The logical product gate array typically first executes an AND (or NAND) operation for a plurality of logical inputs applied thereto from outside. Next the logical summation gate array executes an OR (or NOR) operation for a plurality of logical outputs produced from the logical product gate array. A logical output satisfying predetermined logic conditions can thus be obtained from the logical summation gate array. In this instance, the logic conditions can be set as required in advance by the wiring of the internal circuits of each of the logical product and logical summation gate arrays. In other words, the logic conditions can be programmed.
In a PLA of this kind, however, a large number of switching elements are used, particularly in the logical product gate array. If the PLA is constituted by the bipolar type of active elements, therefore, an extremely large number of bipolar active elements must be formed as the switching elements. Even if IIL (Integrated Injection Logic) devices with a multi-electrode structure are used to reduce the number of elements, an extremely large number of elements are still necessary because the number of electrodes that can be formed on one IIL device is limited. In order to actuate an IIL device, a constant current called an "injection current" must always flow through all the IIL elements, so that the power consumption of the PLA as a whole is very large. Furthermore, as the size of the gate increases, the number of IIL device connected to each IIL device becomes greater. For this reason, the output capacity of each IIL device, that is, its "fan-out", must be increased with the result that the power consumption and size of each IIL device must be further increased. This means that it is considered impossible in practical devices to obtain a large gate size with a PLA of this kind, because of this great increase in the power consumption and drop in the integration density.
The present invention is directed to solving these problems in the prior-art technique.